Montreal, Canada

Félix Dubé

Félix Dubé outdoors in winter — ski goggles and a knit headband, beard and neck gaiter caked in frost, a pack over one shoulder and snowy conifers behind.
An Ethernet frame start in NRZ: the 1010 preamble a receiver locks onto, the start-frame delimiter, then the payload bytes 0x46 0x50 0x47 0x41 — "FPGA".

Senior FPGA Design & Verification Engineer

I design and verify FPGAs for a low-latency trading platform at DRW — market data parsers, network accelerators, and the microwave, millimeter-wave, and HF modems that carry the traffic between them. Before that I led verification of the central electronic unit of a SAR imaging satellite at MDA.

Now
DRW, Montreal / since 2022
Before
MDA / General Electric / McGill University
Focus
Low-latency trading systems / wireless communications / functional verification
Toolchain
SystemVerilog (UVM, SVA) / VHDL / Python (cocotb, pyuvm) / Vivado, Questa
Studied
B.Eng. Electrical Engineering, minor in Software Engineering — McGill University